The Implications of Ferroelectric FET Device Models to the Design of Computing-in-Memory Architectures


 Data transfer between a processor and memory frequently represents bottleneck with respect to improving application-level performance. Computing-in-memory (CiM), where logic arithmetic operations are performed in memory, could significantly reduce both energy consumption computational overheads associated data transfer. This work presents revisited study of FeFET-CiM, CiM architecture capable performing Boolean ((N)AND, (N)OR, X(N)OR, INV) as well (ADD) words memory. In this study, we employ two types FeFET-based cells the architecture. Namely, 2T+1FeFET 1-FeFET cells. The use these FeFET-CiM is enabled by distinct models for FeFET devices. based on 2T+1FeFETs (1FeFETs) offers an average speedup ∼2.5X (∼1.1X) reduction ∼1.7X (∼1.4X) when compared SRAM baseline across 12 benchmark programs. Despite smaller speedups savings 1FeFET-CiM 2T+1FeFET-CiM, 1FeFET arrays may offer up ∼5.3X density improvements conventional 6T-SRAM arrays. Furthermore, significant counterpart STT-CiM architecture.